1. The Field of the Invention
The present invention involves an etching process that utilizes an undoped silicon dioxide layer as an etch mask during a selective etch of a doped silicon dioxide layer that is situated on a semiconductor substrate. More particularly, the present invention relates to a process for depositing and patterning an undoped silicon dioxide layer over a doped silicon dioxide layer and conducting an etching process that is selective to undoped silicon dioxide, but not selective to doped silicon dioxide.
2. The Relevant Technology
Modern integrated circuits are manufactured by an elaborate process in which a large number of electronic semiconductor devices are integrally formed on a semiconductor substrate. In the context of this document, the term xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above. The term doped silicon dioxide refers to a dopant concentration of at least 3 percent by weight of silicon dioxide. The term undoped silicon dioxide refers to a dopant concentration of less than 3 percent by weight of silicon dioxide.
Conventional semiconductor devices which are formed on a semiconductor substrate include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor substrate. In order to compactly form the semiconductor devices, the semiconductor devices are formed on varying levels of the semiconductor substrate. This requires forming a semiconductor substrate with a topographical design.
One common process for forming a topographical design on a semiconductor substrate involves etching of semiconductor material. Etching is typically conducted by depositing and patterning a layer of a masking material over the semiconductor material to be etched. The pattern formed on the layer of masking material defines a series of openings in the masking material and corresponds to the topographical design to be formed during the etching process. Next, an etching agent is applied to the semiconductor material through the pattern openings. In order to successfully form the topographical design, the etching agent must be selective to the masking material and not selective to the semiconductor material to be etched. In other words, the etching agent must remove a portion of the semiconductor material while leaving the masking material substantially intact.
Currently, photoresist material is commonly used as an etch mask. Use of photoresist material in an etch process involves depositing and patterning the photoresist material, applying an etching agent, and removing the photoresist material. Etching is performed using any of a number of processes known in the art, including gaseous, plasma and wet etch processes.
Sometimes double layers of photoresist material are required for forming topographical features. For example, a topographical structure design might call for successive etch processes on upper layers in a first region and a second region of the semiconductor material, then the bottom layers in the first region only. In such a case, a patterned photoresist layer is deposited (on the upper layer) with openings at both the first and second regions. The upper layers are first etched in the opening at the first and second regions. Next, a second patterned photoresist layer is positioned on the first layer. The second layer has openings only in the first region, but covers the second region. An etch agent then removes semiconductor materials of the bottom layers only in the first region. The second region is protected by photoresist so that the bottom layers in this second region will not be etched.
Each step required for forming topographical features on a semiconductor material makes the finished product more expensive to produce. Application and removal of photoresist material or other masking material as currently practiced in semiconductor device manufacturing adds expense and complexity to the process.
It is apparent that it would be advantageous to provide an etch mask that does not need to be removed after the etching process is finished. Additionally, it would be advantageous to provide an etching process that eliminates using two layers of photoresist material in situations where two are presently required. A process is also needed for etching semiconductor material located under existing topographical structures where traditional masking materials cannot be applied and removed or where it would be cumbersome to do so.
The present invention relates to a process for selectively etching a semiconductor material to form a designated topographical structure thereon utilizing an undoped silicon dioxide layer as an etch mask. In one embodiment, a doped silicon dioxide layer is formed over a semiconductor substrate. An undoped silicon dioxide layer is then formed and patterned over the doped silicon dioxide layer. The pattern on the undoped silicon dioxide layer comprises one or more openings, trenches, or other similar structures and exposes a portion of the doped silicon dioxide layer. The doped silicon dioxide layer is selectively removed through the pattern to form an opening, thereby creating a topographical structure using any etching agent that is selective to undoped silicon dioxide, but not selective to doped silicon dioxide. Preferably, a plasma etching process is used. The undoped silicon dioxide layer acts as an etch mask during the etching process. This embodiment provides the advantage that the undoped silicon dioxide layer does not need to be removed after the etching process is completed.
The process in this embodiment may be practiced with or without interleaving layers between the doped and undoped silicon dioxide layers. These interleaving layers may be any of a number of materials including a conductor material and a refractory metal silicide. Optionally, another undoped silicon dioxide layer may be positioned under the doped silicon dioxide layer to serve as an etch stop during etching.
In another embodiment of the present invention, an undoped silicon dioxide layer is used as an etch mask in combination with a photoresist layer for successive etching of a first and a second region on a doped silicon dioxide layer. In this embodiment, a doped silicon dioxide layer is formed over a semiconductor substrate. An undoped silicon dioxide layer is formed and patterned over the doped silicon dioxide layer to provide openings over both the first and second regions. Next, a photoresist layer is deposited over the undoped silicon dioxide layer. The photoresist layer is patterned to provide openings over the first region, while covering the second region.
In this embodiment, the doped silicon dioxide is etched in the first region. The etchant used is not selective to doped silicon dioxide, but is selective to undoped silicon dioxide and to photoresist material. Next, the photoresist layer is stripped, exposing the pattern openings over the second region. Finally, the second region is etched while the undoped silicon dioxide layer acts as an etch mask. This process provides the advantage of using only one layer of photoresist material instead of two as has conventionally been needed.
In still another embodiment of the invention, a lower series of gate stacks is formed over a semiconductor substrate. A doped silicon dioxide layer is deposited over the lower series of gate stacks. Next, an upper series of gate stacks is formed over the doped silicon dioxide layer. Each gate stack belonging to the upper series has a cap composed of substantially undoped silicon dioxide that defines the gate stack""s top surface. Preferably, each gate stack belonging to the lower series also has a cap composed of substantially undoped silicon dioxide, but may have a cap of some other suitable material, such as silicon nitride.
The gate stacks have a multi-layer structure which may comprise a gate oxide situated over a silicon substrate; a polysilicon layer over the gate oxide; and a refractory metal silicide, preferably tungsten silicide, over the polysilicon and under the cap. The gate stacks also have spacers preferably made of substantially undoped silicon dioxide.
The gate stacks of the upper series are preferably aligned parallel to one another. The gate stacks of the lower series are also preferably in parallel alignment. The upper series of gate stacks may be aligned parallel to, orthogonal to, or otherwise in relation to the lower series of gate stacks.
This embodiment further involves applying an etchant to the doped silicon dioxide through spaces provided between the gate stacks. The etchant is not selective to doped silicon dioxide, but is selective to undoped silicon dioxide. The caps of the upper series of gate stacks therefore act as an etch mask in this embodiment. Likewise, if undoped silicon dioxide caps have been used on the lower series of gate stacks act, these caps act as an etch stop. Moreover, undoped silicon dioxide spacers of the upper and lower series of gate stacks may act as etch masks and etch stops, respectively. This embodiment provides the advantage of allowing the above-described structure to be formed where conventional etch mask materials could not be applied or where it would be especially difficult to do so.
The present invention contemplates novel structures formed by use of the inventive process. In particular, the process is used to form a lower series of parallel gate stacks overlaid by an upper series of gate stacks, each gate stack having an undoped silicon dioxide cap and undoped silicon dioxide spacers. In a preferred embodiment, the upper series of gate stacks is orthogonal to the lower series of gate stacks. The gate stacks of the upper series may serve as bit lines, while the gate stacks of the lower series may be word lines.